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a functional block diagram AD7713 ain2(+) ain2(? ain3 standby clock generation serial interface control register output register charging balancing a/d converter auto-zeroed ? - d modulator digital filter agnd dgnd mode sdata sclk a0 mclk out mclk in ain1(+) ain1(? ref in(? ref in(+) av dd dv dd av dd 1? a = 1 ?128 av dd 200? v bias sync drdy tfs rfs rtd2 pga 200? rtd1 input scaling m u x features charge balancing adc 24 bits no missing codes 6 0.0015% nonlinearity three-channel programmable gain front end gains from 1 to 128 two differential inputs one single ended high voltage input low-pass filter with programmable filter cutoffs ability to read/write calibration coefficients bidirectional microcontroller serial interface single supply operation low power (3.5 mw typ) with power-down mode (150 m w typ) applications loop powered (smart) transmitters rtd transducers process control portable industrial instruments lc 2 mos loop-powered signal conditioning adc rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. AD7713* ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 cmos construction ensures low power dissipation and a hard- ware programmable power-down mode reduces the standby power consumption to only 150 m w typical. the part is avail- able in a 24-pin, 0.3 inch wide, plastic and hermetic dual-in-line package (dip) as well as a 24-lead small outline (soic) package. product highlights 1. the AD7713 consumes less than 1 ma in total supply cur- rent, making it ideal for use in loop-powered systems. 2. the two programmable gain channels allow the AD7713 to accept input signals directly from a transducer removing a considerable amount of signal conditioning. to maximize the flexibility of the part, the high level analog input accepts 4 v ref signals. on-chip current sources provide excitation for three-wire and four-wire rtd configurations. 3. no missing codes ensures true, usable, 24-bit dynamic range coupled with ex cellent 0.0015% accuracy. the effects of temperature drift are eliminated by on-chip self-calibration, which removes zero-scale and full-scale errors. 4. the AD7713 is ideal for microcontroller or dsp processor applications with an on-chip control register which allows control over filter cutoff, input gain, signal polarity and cali- bration modes. the AD7713 allows the user to read and write the on-chip calibration registers. general description the AD7713 is a complete analog front end for low frequency measurement applications. the device accepts low level signals directly from a transducer or high level signals (4 v ref ) and outputs a serial digital word. it employs a sigma-delta con- version technique to realize up to 24 bits of no missing codes performance. the input signal is applied to a proprietary pro- grammable gain front end based around an analog modulator. the modulator output is processed by an on-chip digital filter. the first notch of this digital filter can be programmed via the on-chip control register allowing adjustment of the filter cutoff and settling time. the part features two differential analog inputs and one single- ended high level analog input as well as a differential reference input. it can be operated from a single supply (av dd and dv dd at +5 v). the part provides two current sources which can be used to provide excitation in three-wire and four-wire rtd con- figurations. the AD7713 thus performs all signal conditioning and conversion for a single, dual or three-channel system. the AD7713 is ideal for use in smart, microcontroller-based systems. gain settings, signal polarity and rtd current control can be configured in software using the bidirectional serial port. the AD7713 contains self-calibration, system calibration and background calibration options and also allows the user to read and to write the on-chip calibration registers. *protected by u.s. patent no. 5,134,401.
parameter a, s versions 1 units conditions/comments static performance no missing codes 24 bits min guaranteed by design. for filter notches 12 hz 22 bits min for filter notch = 20 hz 18 bits min for filter notch = 50 hz 15 bits min for filter notch = 100 hz 12 bits min for filter notch = 200 hz output noise see tables i & ii depends on filter cutoffs and selected gain integral nonlinearity 0.0015 % of fsr max filter notches 12 hz; typically 0.0003% positive full-scale error 2, 3 see note 4 full-scale drift 5 1 m v/ c typ for gains of 1, 2 0.3 m v/ c typ for gains of 4, 8, 16, 32, 64, 128 unipolar offset error 2 see note 4 unipolar offset drift 5 0.5 m v/ c typ for gains of 1, 2 0.25 m v/ c typ for gains of 4, 8, 16, 32, 64, 128 bipolar zero error 2 see note 4 bipolar zero drift 5 0.5 m v/ c typ for gains of 1, 2 0.25 m v/ c typ for gains of 4, 8, 16, 32, 64, 128 gain drift 2 ppm/ c typ bipolar negative full-scale error 2 0.004 % of fsr max typically 0.0006% bipolar negative full-scale drift 5 1 m v/ c typ for gains of 1, 2 0.3 m v/ c typ for gains of 4, 8, 16, 32, 64, 128 analog inputs input sampling rate, f s see table iii normal-mode 50 hz rejection 6 100 db min for filter notches of 2 hz, 5 hz, 10 hz, 25 hz, 50 hz, 0.02 f notch normal-mode 60 hz rejection 6 100 db min for filter notches of 2 hz, 6 hz, 10 hz, 30 hz, 60 hz, 0.02 f notch ain1, ain2 7 input voltage range 8 for normal operation. depends on gain selected. 0 to +v ref 9 v max unipolar input range (b/u bit of control register = 1) v ref v max bipolar input range (b/u bit of control register = 0) common-mode rejection (cmr) 100 db min at dc common-mode 50 hz rejection 6 150 db min for filter notches of 2 hz, 5 hz, 10 hz, 25 hz, 50 hz, 0.02 f notch common-mode 60 hz rejection 6 150 db min for filter notches of 2 hz, 6 hz, 10 hz, 30 hz, 60 hz, 0.02 f notch common-mode voltage range 10 agnd to av dd v min to v max dc input leakage current @ +25 c 10 pa max t min to t max 1 na max sampling capacitance 6 20 pf max ain3 input voltage range 0 to + 4 v ref v max for normal operation. depends on gain selected gain error 11 0.05 % typ additional error contributed by resistor attenuator gain drift 1 ppm/ c typ additional drift contributed by resistor attenuator offset error 11 4 mv max additional error contributed by resistor attenuator input impedance 30 k w min notes 1 temperature range is as follows: a version, C40 c to +85 c; s version, C55 c to +125 c. 2 applies after calibration at the temperature of interest. 3 positive full-scale error applies to both unipolar and bipolar input ranges. 4 these errors will be of the order of the output noise of the part as shown in table i after system calibration. these errors will be 20 m v typical after self-calibration or background calibration. 5 recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6 these numbers are guaranteed by design and/or characterization. 7 the ain1 and ain2 analog inputs presents a very high impedance dynamic load which varies with clock frequency and input sample rate. the maximum recommended source resistance depends on the selected gain. 8 the analog input voltage range on the ain1(+) and ain2(+) inputs is given here with respect to the voltage on the ain1(C) and ain2 (C) inputs. the input voltage range on the ain3 input is with respect to agnd. the absolute voltage on the ain1 and ain2 inputs should not go more positive than a v dd + 30 mv or more negative than agnd C 30 mv. 9 v ref = ref in(+) C ref in(C). 10 this common-mode voltage range is allowed provided that the input voltage on ain(+) and ain(C) does not exceed a v dd + 30 mv and agnd C 30 mv. 11 this error can be removed using the system calibration capabilities of the AD7713. this error is not removed by the AD7713s self-calibration feature. the offset drift on the ain3 input is four times the value given in the static performance section. C2C rev. c (av dd = +5 v 6 5%; dv dd = +5 v 6 5%; ref in(+) = +2.5 v; ref in(C) = agnd; mclk in = 2 mhz unless otherwise noted. all specifications t min to t max unless otherwise noted.) AD7713Cspecifications
parameter a, s versions 1 units conditions/comments reference input ref in(+) C ref in(C) voltage +2.5 to av dd /1.8 v min to v max for specified performance. part is functional with lower v ref voltages input sampling rate, f s f clk in /512 normal-mode 50 hz rejection 6 100 db min for filter notches of 2 hz, 5 hz, 10 hz, 25 hz, 50 hz, 0.02 f notch normal-mode 60 hz rejection 6 100 db min for filter notches of 2 hz, 6 hz, 10 hz, 30 hz, 60 hz, 0.02 f notch common-mode rejection (cmr) 100 db min at dc common-mode 50 hz rejection 6 150 db min for filter notches of 2 hz, 5 hz, 10 hz, 25 hz, 50 hz, 0.02 f notch common-mode 60 hz rejection 6 150 db min for filter notches of 2 hz, 6 hz, 10 hz, 30 hz, 60 hz, 0.02 f notch common-mode voltage range 10 agnd to av dd v min to v max dc input leakage current @ +25 c 10 pa max t min to t max 1 na max logic inputs input current 10 m a max all inputs except mclk in v inl , input low voltage 0.8 v max v inh , input high voltage 2.0 v min mclk in only v inl , input low voltage 0.8 v max v inh , input high voltage 3.5 v min logic outputs v ol , output low voltage 0.4 v max i sink = 1.6 ma v oh , output high voltage 4.0 v min i source = 100 m a floating state leakage current 10 m a max floating state output capacitance 12 9 pf typ transducer burn-out current 1 m a nom initial tolerance @ +25 c 10 % typ drift 0.1 %/ c typ rtd excitation currents (rtd1, rtd2) output current 200 m a nom initial tolerance @ +25 c 20 % max drift 20 ppm/ c typ initial matching @ +25 c 1 % max matching between rtd1 and rtd2 currents drift matching 3 ppm/ c typ matching between rtd1 and rtd2 current drift line regulation (av dd ) 200 na/v max av dd = +5 v load regulation 200 na/v max system calibration ain1, ain2 positive full-scale calibration limit 13 +(1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) negative full-scale calibration limit 13 C(1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) offset calibration limit 14, 15 C(1.05 v ref )/gain v max gain is the selected pga gain (between 1 and 128) input span 14 +0.8 v ref /gain v min gain is the selected pga gain (between 1 and 128) +(2.1 v ref )/gain v max gain is the selected pga gain (between 1 and 128) ain3 positive full-scale calibration limit 13 +(4.2 v ref )/gain v max gain is the selected pga gain (between 1 and 128) offset calibration limit 15 0 to v ref /gain v max gain is the selected pga gain (between 1 and 128) input span +3.2 v ref /gain v min gain is the selected pga gain (between 1 and 128) +(4.2 v ref )/gain v max gain is the selected pga gain (between 1 and 128) notes 12 guaranteed by design, not production tested. 13 after calibration, if the analog input exceeds positive full scale, the converter will output all 1s. if the analog input is less than negative full scale, then the device will output all 0s. 14 these calibration and span limits apply provided the absolute voltage on the ain1 and ain2 analog inputs does not exceed av dd + 30 mv or go more negative than agnd C 30 mv. 15 the offset calibration limit applies to both the unipolar zero point and the bipolar zero point. AD7713 C3C rev. c
parameter a, s versions 1 units conditions/comments power requirements power supply voltages av dd voltage +5 to +10 v nom 5% for specified performance dv dd voltage 16 +5 v nom 5% for specified performance power supply currents av dd current 0.6 ma max av dd = +5 v 0.7 ma max av dd = +10 v dv dd current 0.5 ma max f clk in = 1 mhz. digital inputs 0 v to dv dd 1 ma max f clk in = 2 mhz. digital inputs 0 v to dv dd power supply rejection 17 rejection w.r.t. agnd (av dd and dv dd ) see note 18 db typ power dissipation normal mode 5.5 mw max av dd = dv dd = +5 v, f clk in = 1 mhz; typically 3.5 mw standby (power-down) mode 300 m w max av dd = dv dd = +5 v, typically 150 m w notes 16 the 5% tolerance on the dv dd input is allowed provided that dv dd does not exceed av dd by more than 0.3 v. 17 measured at dc and applies in the selected passband. psrr at 50 hz will exceed 120 db with filter notches of 2 hz, 5 hz, 10 hz, 25 hz or 50 hz. psrr at 60 hz will exceed 120 db with filter notches of 2 hz, 6 hz, 10 hz, 30 hz or 60 hz. 18 psrr depends on gain: gain of 1 = 70 db typ; gain of 2 = 75 db typ; gain of 4 = 80 db typ; gains of 8 to 128 = 85 db typ. specifications subject to change without notice. AD7713Cspecifications rev. c C4C timing characteristics 1, 2 limit at t min , t max parameter (a, s versions) units conditions/comments f clk in 3, 4 400 khz min master clock frequency: crystal oscillator or 2 mhz max externally supplied for specified performance t clk in lo 0.4 t clk in ns min master clock input low time; t clk in = 1/f clk in t clk in hi 0.4 t clk in ns min master clock input high time t r 5 50 ns max digital output rise time; typically 20 ns t f 5 50 ns max digital output fall time; typically 20 ns t 1 1000 ns min sync pulse width self-clocking mode t 2 0 ns min drdy to rfs setup time t 3 0 ns min drdy to rfs hold time t 4 2 t clk in ns min a0 to rfs setup time t 5 0 ns min a0 to rfs hold time t 6 4 t clk in + 20 ns max rfs low to sclk falling edge t 7 6 4 t clk in +20 ns max data access time ( rfs low to data valid) t 8 6 t clk in /2 ns min sclk falling edge to data valid delay t clk in /2 + 30 ns max t 9 t clk in /2 ns nom sclk high pulse width t 10 3 t clk in /2 ns nom sclk low pulse width t 14 50 ns min a0 to tfs setup time t 15 0 ns min a0 to tfs hold time t 16 4 t clk in + 20 ns max tfs to sclk falling edge delay time t 17 4 t clk in ns min tfs to sclk falling edge hold time t 18 0 ns min data valid to sclk setup time t 19 10 ns min data valid to sclk hold time (dv dd = +5 v 5%; av dd = +5 v or +10 v 5%; agnd = dgnd = 0 v; f clkin =2 mhz; input logic 0 = 0 v, logic 1 = dv dd unless otherwise noted.)
2 C5C rev. c AD7713 limit at t min , t max parameter (a, s versions) units conditions/comments external-clocking mode f sclk f clk in /5 mhz max serial clock input frequency t 20 0 ns min drdy to rfs setup time t 21 0 ns min drdy to rfs hold time t 22 2 t clk in ns min a0 to rfs setup time t 23 0 ns min a0 to rfs hold time t 24 6 4 t clk in ns max data access time ( rfs low to data valid) t 25 6 10 ns min sclk falling edge to data valid delay 2 t clk in + 20 ns max t 26 2 t clk in ns min sclk high pulse width t 27 2 t clk in ns min sclk low pulse width t 28 t clk in + 10 ns max sclk falling edge to drdy high t 29 7 10 ns min sclk to data valid hold time t clk in + 10 ns max t 30 10 ns min rfs / tfs to sclk falling edge hold time t 31 7 5 t clk in /2 + 50 ns max rfs to data valid hold time t 32 0 ns min a0 to tfs setup time t 33 0 ns min a0 to tfs hold time t 34 4 t clk in ns min sclk falling edge to tfs hold time t 35 2 t clk in C sclk high ns min data valid to sclk setup time t 36 30 ns min data valid to sclk hold time notes 1 guaranteed by design, not production tested. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 see figures 10 to 13. 3 clk in duty cycle range is 45% to 55%. clk in must be supplied whenever the AD7713 is not in standby mode. if no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4 the AD7713 is production tested with f clk in at 2 mhz. it is guaranteed by characterization to operate at 400 khz. 5 specified using 10% and 90% points on waveform of interest. 6 these numbers are measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 2.4 v. 7 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove effects of charging or discharging the 100 pf capacitor. this means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. to output pin +2.1v 1.6ma 200? 100pf figure 1. load circuit for access time and bus relinquish time
rev. c C6C AD7713 junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150 c plastic dip package, power dissipation . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 105 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . . +260 c cerdip package, power dissipation . . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . 70 c/w lead temperature, soldering . . . . . . . . . . . . . . . . . . . +300 c soic package, power dissipation . . . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c power dissipation (any package) to +75 c . . . . . . . . . 450 mw *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* (t a = +25 c, unless otherwise noted) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +12 v av dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +12 v dv dd to agnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v ain1, ain2 input voltage to agnd . . . . . . . . . . . . . . . . . . . . . C0.3 v to av dd + 0.3 v ain3 input voltage to agnd . . . . . . . . . . . . C0.3 v to +22 v reference input voltage to agnd . . C 0.3 v to av dd + 0.3 v digital input voltage to dgnd . . . . C 0.3 v to av dd + 0.3 v digital output voltage to dgnd . . . C 0.3 v to dv dd + 0.3 v operating temperature range commercial (a version) . . . . . . . . . . . . . . . C40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v, which readily accumulate on the human body and on test equipment, can discharge without detection. although devices feature proprietary esd protection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic discharges. therefore, proper precautions are recommended to avoid any performance degradation or loss of functionality. ordering guide model temperature range package option* AD7713an C40 c to +85 c n-24 AD7713ar C40 c to +85 c r-24 AD7713aq C40 c to +85 c q-24 AD7713sq C55 c to +125 c q-24 eval-AD7713eb evaluation board *n = plastic dip; q = cerdip; r = soic. pin configuration dip and soic 13 16 15 14 24 23 22 21 20 19 18 17 top view (not to scale) 12 11 10 9 8 1 2 3 4 7 6 5 AD7713 sclk drdy sdata dv dd dgnd mclk in mclk out a0 agnd tfs rfs sync mode ain1(+) ain1(? ain2(+) ain2(? ref in(+) rtd2 ain3 standby av dd ref in(? rtd1
2 C7C rev. c AD7713 pin function description pin mnemonic function 1 sclk serial clock. logic input/output depending on the status of the mode pin. when mode is high, the device is in its self-clocking mode and the sclk pin provides a serial clock output. this sclk becomes active when rfs or tfs goes low and it goes high impedance when either rfs or tfs returns high or when the device has completed transmission of an output word. when mode is low, the device is in its external clocking mode and the sclk pin acts as an input. this input serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. alternatively, it can be a noncontinuous clock with the information being transmitted to the AD7713 in smaller batches of data. 2 mclk in master clock signal for the de vice. t his can be provided in the form of a crystal or external clock. a crys tal can be tied across the mclk in and mclk out pins. alternatively, the mclk in pin can be driven with a cmos-compatible clock and mclk out left unconnected. the clock input frequency is nominally 2 mhz. 3 mclk out when the m aster clock for the device is a crystal, the crystal is connected between mclk in and mclk out. 4 a0 addr ess input. with this input low, reading and writing to the device is to the control register. with this input high, access is to either the data register or the calibration registers. 5 sync logic in put which allows for synchronization of the digital filters when using a number of ad771 3s. it resets the nodes of the digital filter. 6 mode logic input. w hen this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its external clocking mode. 7 ain1(+) analog input channel 1. positive input of the programmable gain differential analog input. the ain1(+) input is connected to an output current source which can be used to check that an external transducer has burnt out or gone open circuit. this output current source can be turned on/off via the control register. 8 ain1(C) analog input channel 1. negative input of the programmable gain differential analog input. 9 ain2(+) analog input channel 2. positive input of the programmable gain differential analog input. 10 ain2(C) analog input channel 2. negative input of the programmable gain differential analog input. 11 standby logic input. taking this pin low shuts down the internal analog and digital circuitry, reducing power consumption to less than 50 m w. 12 av dd analog positive supply voltage, +5 v to +10 v. 13 rtd1 constant current output. a nominal 200 m a constant current is provided at this pin and this can be used as the excitation current for rtds. this, current can be turned on or off via the control register. 14 ref in(C) reference input. the ref in(C) can lie anywhere between av dd and agnd provided ref in(+) is greater than ref in(C). 15 ref in(+) reference input. the reference input is differential providing that ref in(+) is greater than ref in(C). ref in(+) can lie anywhere between av dd and agnd. 16 rtd2 constant current output. a nominal 200 m a constant current is provided at this pin and this can be used as the excitation current for rtds. this, current can be turned on or off via the control register. this second current can be used to eliminate lead resistanced errors in three-wire rtd configurations. 17 ain3 analog input channel 3. high level analog input which accepts an analog input voltage range of 4 v ref /gain. at the nominal v ref of +2.5 v and a gain of 1, the ain3 input voltage range is 0 to 10 v. 18 agnd ground reference point for analog circuitry. 19 tfs transmit frame synchronization. active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. in the self-clocking mode, the serial clock becomes active after tfs goes low. in the external clocking mode, tfs must go low before the first bit of the data word is written to the part. 20 rfs receive frame synchronization. active low logic input used to access serial data from the device. in the self-clocking mode, the sclk and sdata lines both become active after rfs goes low. in the external clocking mode, the sdata line becomes active after rfs goes low.
rev. c C8C AD7713 pin mnemonic function 21 drdy logic output. a falling edge indicates that a new output word is available for transmission. the drdy pin will return high upon completion of transmission of a full output word. drdy is also used to indicate when the AD7713 has completed its on-chip calibration sequence. 22 sdata serial data. input/output with serial data being written to either the control register or the calibration registers and serial data being accessed from the control register, calibration registers or the data register. during an output data read operation, serial data becomes active after rfs goes low (provided drdy is low). during a write operation, valid serial data is expected on the rising edges of sclk when tfs is low. the output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs. 23 dv dd digital supply voltage, +5 v. dv dd should not exceed av dd by more than 0.3 v in normal operation. 24 dgnd ground reference point for digital circuitry. terminology integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the end- points of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 lsb below the first code transi- tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 lsb above the last code transition (111 . . . 110 to 111 . . . 111). the error is expressed as a percentage of full scale. positive full-scale error positive full-scale error is the deviation of the last code transi- tion (111 . . . 110 to 111 . . . 111) from the ideal input full-scale voltage. for ain1(+) and ain2(+), the ideal full-scale input voltage is (ain1(C) + v ref /gain C 3/2 lsbs) where ain(C) is either ain1(C) or ain2(C) as appropriate; for ain3, the ideal full-scale voltage is +4 v ref /gain C 3/2 lsbs. positive full- scale error applies to both unipolar and bipolar analog input ranges. unipolar offset error unipolar offset error is the deviation of the first code transition from the ideal voltage. for ain1(+) and ain2(+), the ideal input voltage is (ain1(C) + 0.5 lsb); for ain3, the ideal input is 0.5 lsb when operating in the unipolar mode. bipolar zero error this is the deviation of the midscale transition (0111 ...111 to 1000 . . . 000) from the ideal input voltage. for ain1(+) and ain2(+), the ideal input voltage is (ain1(C) C 0.5 lsb); ain3 can only accommodate unipolar input ranges. bipolar negative full-scale error this is the deviation of the first code transition from the ideal input voltage. for ain1(+) and ain2(+), the ideal input volt- age is (ain1(C) C v ref /gain + 0.5 lsb); ain3 can only ac- commodate unipolar input ranges. positive full-scale overrange positive full-scale overrange is the amount of overhead available to handle input voltages on ain1(+) and ain2(+) inputs greater than (ain1(C) + v ref /gain) or on ain3 of greater than +4 v ref /gain (for example, noise peaks or excess volt- ages due to system gain errors in system calibration routines) without introducing errors due to overloading the analog modu- lator or to overflowing the digital filter. negative full-scale overrange this is the amount of overhead available to handle voltages on ain1(+) and ain2(+) below (ain1(C) C v ref /gain) without overloading the analog modulator or overflowing the digital filter. offset calibration range in the system calibration modes, the AD7713 calibrates its offset with respect to the analog input. the offset calibration range specification defines the range of voltages that the AD7713 can accept and still calibrate offset accurately. full-scale calibration range this is the range of voltages that the AD7713 can accept in the system calibration mode and still calibrate full scale correctly. input span in system calibration schemes, two voltages applied in sequence to the AD7713s analog input define the analog input range. the input span specification defines the minimum and maxi- mum input voltages from zero to full scale that the AD7713 can accept and still calibrate gain accurately.
2 C9C rev. c AD7713 control register (24 bits) a write to the device with the a0 input low writes data to the control register. a read to the device with the a0 input low accesses the contents of the control register. the control register is 24 bits wide and when writing to the register 24 bits of data must be written otherwise the data will not be loaded to the control register. in other words, it is not possible to write just the first 12 bits of data into the control register. if more than 24 clock pulses are provided before tfs returns high, then all clock pulses after the 24th clock pulse are ignored. similarly, a read operation from the control register should access 24 bits of data. msb md2 md1 md0 g2 g1 g0 ch1 ch0 wl ro bo b/u fs11 fs10 fs9 fs8 fs7 fs6 fs5 fs4 fs3 fs2 fs1 fs0 lsb operating mode md2 md1 md0 operating mode 0 0 0 normal mode. this is the normal mode of operation of the device whereby a read to the device with a0 high accesses data from the data register. this is the default condition of these bits after the internal power-on reset. 0 0 1 activate self-calibration. this activates self-calibration on the channel selected by ch0 and ch1. this is a one-step calibration sequence, and when complete, the part returns to normal mode (with md2, md1, md0 of the control registers returning to 0, 0, 0). the drdy output indicates when this self- calibration is complete. for this calibration type, the zero-scale calibration is done internally on shorted (zeroed) inputs and the full-scale calibration is done on v ref . 0 1 0 activate system calibration. this activates system calibration on the channel selected by ch0 and ch1. this is a two-step calibration sequence, with the zero-scale calibration done first on the selected input channel and drdy indicating when this zero-scale calibration is complete. the part returns to normal mode at the end of this first step in the two-step sequence. 0 1 1 activate system calibration. this is the second step of the system calibration sequence with full-scale calibration being performed on the selected input channel. once again, drdy indicates when the full- scale calibration is complete. when this calibration is complete, the part returns to normal mode. 1 0 0 activate system offset calibration. this activates system offset calibration on the channel selected by ch0 and ch1. this is a one-step calibration sequence and, when complete, the part returns to normal mode with drdy indicating when this system offset calibration is complete. for this calibration type, the zero-scale calibration is done on the selected input channel and the full-scale calibration is done internally on v ref . 1 0 1 activate background calibration. this activates background calibration on the channel selected by ch0 and ch1. if the background calibration mode is on, then the AD7713 provides continuous self- calibration of the reference and shorted (zeroed) inputs. this calibration takes place as part of the con- version sequence, extending the conversion time and reducing the word rate by a factor of six. its major advantage is that the user does not have to worry about recalibrating the device when there is a change in the ambient temperature. in this mode, the shorted (zeroed) inputs and v ref , as well as the analog input voltage, are continuously monitored and the calibration registers of the device are updated. 1 1 0 read/write zero-scale calibration coefficients. a read to the device with a0 high accesses the contents of the zero-scale calibration coefficients of the channel selected by ch0 and ch1. a write to the device with a0 high writes data to the zero-scale calibration coefficients of the channel selected by ch0 and ch1. the word length for reading and writing these coefficients is 24 bits, regardless of the status of the wl bit of the control register. therefore, when writing to the calibration register, 24 bits of data must be written, otherwise the new data will not be transferred to the calibration register. 1 1 1 read/write full-scale calibration coefficients. a read to the device with a0 high accesses the contents of the full-scale calibration coefficients of the channel selected by ch0 and ch1. a write to the device with a0 high writes data to the full-scale calibration coefficients of the channel selected by ch0 and ch1. the word length for reading and writing these coefficients is 24 bits, regardless of the status of the wl bit of the control register. therefore, when writing to the calibration register, 24 bits of data must be written, otherwise the new data will not be transferred to the calibration register.
rev. c C10C AD7713 pga gain g2 gl g0 gain 0 0 0 1 (default condition after the internal power-on reset) 00 1 2 01 0 4 01 1 8 10 0 16 10 1 32 11 0 64 1 1 1 128 channel selection ch1 ch0 channel 0 0 ain1 (default condition after the internal power-on reset) 0 1 ain2 1 0 ain3 word length wl output word length 0 16-bit (default condition after internal power-on reset) 1 24-bit rtd excitation currents ro 0 off (default condition after internal power-on reset) 1on burn-out current bo 0 off (default condition after internal power-on reset) 1on bipolar/unipolar selection (both inputs) b/u 0 bipolar (default condition after internal power-on reset) 1 unipolar filter selection (fs11Cfs0) the on-chip digital filter provides a sinc 3 (or (sinx/x) 3 ) filter response. the 12 bits of data programmed into these bits determine the filter cutoff frequency, the position of the first notch of the filter and the data rate for the part. in association with the gain selec- tion, it also determines the output noise (and hence the effective resolution) of the device. the first notch of the filter occurs at a frequency determined by the relationship: filter first notch frequency = (f clk in /512)/ code where code is the decimal equivalent of the code in bits fs0 to fs11 and is in the range 19 to 2,000. with the nominal f clk in of 2 mhz, this results in a first notch frequency range from 1.952 hz to 205.59 khz. to ensure correct operation of the AD7713, the value of the code loaded to these bits must be within this range. failure to do this will result in unspecified operation of the device. changing the filter notch frequency, as well as the selected gain, impacts resolution. tables i and ii and figure 2 show the effect of the filter notch frequency and gain on the effective resolution of the AD7713. the output data rate (or effective conversion time) for the device is equal to the frequency selected for the first notch of the filter. for example, if the first notch of the filter is selected at 10 hz, then a new word is available at a 10 hz rate or every 100 ms. if the first notch is at 200 hz, a new word is available every 5 ms. the settling time of the filter to a full-scale step input change is worst case 4 1/(output data rate). this settling time is to 100% of the final value. for example, with the first filter notch at 100 hz, the settling time of the filter to a full-scale step input change is 400 ms max. if the first notch is at 200 hz, the settling time of the filter to a full-scale input step is 20 ms max. this settling time can be reduced to 3 l/(output data rate) by synchronizing the step input change to a reset of the digital filter. in other words, if the step input takes place with sync low, the settling time will be 3 l/(output data rate). if a change of channels takes place, the set- tling time is 3 l/(output data rate) regardless of the sync input. the C3 db frequency is determined by the programmed first notch frequency according to the relationship: filter C3 db frequency = 0.262 first notch frequency.
2 C11C rev. c AD7713 tables i and ii show the output rms noise for some typical notch and C3 db frequencies. the numbers given are for the bipolar in- put ranges with a v ref of +2.5 v. these numbers are typical and are generated with an analog input voltage of 0 v. the output noise from the part comes from two sources. first, there is the electrical noise in the semiconductor devices used in the implementa- tion of the modulator (device noise). secondly, when the analog input signal is converted into the digital domain, quantization noise is added. the device noise is at a low level and is largely independent of frequency. the quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source. consequently, lower filter notch settings (below 12 hz approximately) tend to be device noise dominated while higher notch settings are dominated by quantization noise. changing the filter notch and cutoff frequency in the quantization noise dominated region results in a more dramatic improvement in noise performance than it does in the device noise dominated region as shown in table i. furthermore, quantization noise is added after the pga, so effective resolution is independent of gain for the higher filter notch frequencies. meanwhile, device noise is added in the pga and, therefore, effective resolution suffers a little at high gains for lower notch frequencies. at the lower filter notch settings (below 12 hz), the no missing codes performance of the device is at the 24-bit level. at the higher settings, more codes will be missed until at 200 hz notch setting, no missing codes performance is only guaranteed to the 12-bit level. however, since the effective resolution of the part is 10.5 bits for this filter notch setting, this no missing codes performance should be more than adequate for all applications. the effective resolution of the device is defined as the ratio of the output rms noise to the input full scale. this does not remain con- stant with increasing gain or with increasing bandwidth. table ii shows the same table as table i except that the output is now ex- pressed in terms of effective resolution (the magnitude of the rms noise with respect to 2 v ref /gain, i.e., the input full scale). it is possible to do post filtering on the device to improve the output data rate for a given C3 db frequency and also to further reduce the output noise (see digital filtering section). table i. output noise vs. gain and first notch frequency first notch of typical output rms noise ( m v) filter and o/p C3 db gain of gain of gain of gain of gain of gain of gain of gain of data rate 1 frequency 1248163264128 2hz 2 0.52 hz 1.0 0.78 0.48 0.33 0.25 0.25 0.25 0.25 5hz 2 1.31 hz 1.8 1.1 0.63 0.5 0.44 0.41 0.38 0.38 6hz 2 1.57 hz 2.5 1.31 0.84 0.57 0.46 0.43 0.4 0.4 10 hz 2 2.62 hz 4.33 2.06 1.2 0.64 0.54 0.46 0.46 0.46 12 hz 2 3.14 hz 5.28 2.36 1.33 0.87 0.63 0.62 0.6 0.56 20 hz 3 5.24 hz 13 6.4 3.7 1.8 1.1 0.9 0.65 0.65 50 hz 3 13.1 hz 130 75 25 12 7.5 4 2.7 1.7 100 hz 3 26.2 hz 0.6 10 3 0.26 10 3 140 70 35 25 15 8 200 hz 3 52.4 hz 3.1 10 3 1.6 10 3 0.7 10 3 0.29 10 3 180 120 70 40 notes 1 the default condition (after the internal power-on reset) for the first notch of filter is 60 hz. 2 for these filter notch frequencies, the output rms noise is primarily dominated by device noise and as a result is independent of the value of the reference voltage. therefore, increasing the reference voltage will give an increase in the effective resolution of the device (i.e., the ratio of the rms noise to the input full scale is increased since the output rms noise remains constant as the input full scale increases). 3 for these filter notch frequencies, the output rms noise is dominated by quantization noise and as a result is proportional to the value of the reference voltage. table ii. effective resolution vs. gain and first notch frequency first notch of effective resolution 1 (bits) filter and o/p C3 db gain of gain of gain of gain of gain of gain of gain of gain of data rate frequency 1248163264128 2 hz 0.52 hz 22.5 21.5 21.5 21 20.5 19.5 18.5 17.5 5 hz 1.31 hz 21.5 21 21 20 19.5 18.5 17.5 16.5 6 hz 1.57 hz 21 21 20.5 20 19.5 18.5 17.5 16.5 10 hz 2.62 hz 20 20 20 19.5 19 18.5 17.5 16.5 12 hz 3.14 hz 20 20 20 19.5 19 18 17 16 20 hz 5.24 hz 18.5 18.5 18.5 18.5 18 17.5 17 16 50 hz 13.1 hz 15 15 15.5 15.5 15.5 15.5 15 14.5 100 hz 26.2 hz 13 13 13 13 13 12.5 12.5 12.5 200 hz 52.4 hz 10.5 10.5 11 11 11 10.5 10 10 note 1 effective resolution is defined as the magnitude of the output rms noise with respect to the input full scale (i.e., 2 v ref /gain). the above table applies for a v ref of +2.5 v and resolution numbers are rounded to the nearest 0.5 lsb.
rev. c C12C AD7713 figure 2 gives similar information to that outlined in table i. in this plot, the output rms noise is shown for the full range of avail- able cutoff frequencies rather than for some typical cutoff frequencies as in tables i and ii. the numbers given in these plots are typical values at 25 c. 10 1000 10000 100 notch frequency ?hz 10000 100 0.1 1000 10 1 output noise ?? gain of 1 gain of 2 gain of 4 gain of 8 figure 2a. plot of output noise vs. gain and notch frequency (gains of 1 to 8) circuit description the AD7713 is a sigma-delta a/d converter with on-chip digi- tal filtering, intended for the measurement of wide dynamic range, low frequency signals such as those in industrial control or process control applications. it contains a sigma-delta (or charge balancing) adc, a calibration microcontroller with on- chip static ram, a clock oscillator, a digital filter and a bidirec- tional serial communications port. the part contains three analog input channels, two program- mable gain differential input and one programmable gain high- level single-ended input. the gain range on both inputs is from 1 to 128. for the ain1 and ain2 inputs, this means that the input can accept unipolar signals of between 0 mv to +20 mv and 0 v to +2.5 v or bipolar signals in the range from 20 mv to 2.5 v when the reference input voltage equals +2.5 v. the input voltage range for the ain3 input is +4 v ref /gain and is 0 v to + 10 v with the nominal reference of +2.5 v and a gain of 1. the input signal to the selected analog input channel is continuously sampled at a rate determined by the frequency of the master clock, mclk in, and the selected gain (see table iii). a charge balancing a/d converter (sigma-delta modulator) converts the sampled signal into a digital pulse train whose duty cycle contains the digital information. the program- mable gain function on the analog input is also incorporated in this sigma-delta modulator with the input sampling frequency being modified to give the higher gains. a sinc 3 digital low-pass filter processes the output of the sigma-delta modulator and up- dates the output register at a rate determined by the first notch frequency of this filter. the output data can be read from the serial port randomly or periodically at any rate up to the output register update rate. the first notch of this digital filter (and hence its C3 db frequency) can be programmed via an on-chip control register. the programmable range for this first notch frequency is from 1.952 hz to 205.59 hz, giving a programma- ble range for the C3 db frequency of 0.52 hz to 53.9 hz. the basic connection diagram for the part is shown in figure 3. this shows the AD7713 in the external clocking mode with both the av dd and dv dd pins of the AD7713 being driven notch frequency ?hz 10 1000 10000 100 1000 10 0.1 100 1 0utput noise ?? gain of 16 gain of 32 gain of 64 gain of 128 figure 2b. plot of output noise vs. gain and notch frequency (gain of 16 to 128) from the analog +5 v supply. some applications will have sepa- rate supplies for both av dd and dv dd and in some of these cases the analog s upply will exceed the +5 v digital s upply (see power supplies and grounding section). ref in(+) ain1(+) ain1(? ain3 av dd dv dd agnd dgnd mclk in mclk out sclk sdata drdy tfs rfs ref in(? sync a0 analog +5v supply 10? 0.1? 0.1? AD7713 differential analog input single?nded analog input analog ground digital ground data ready receive (read) serial data serial clock transmit (write) mode dv dd standby address input dv dd ain2(+) ain2(? { differential analog input +2.5v reference { figure 3. basic connection diagram the AD7713 provides a number of calibration options which can be programmed via the on-chip control register. a calibra- tion cycle may be initiated at any time by writing to this control register. the part can perform self-calibration using the on-chip calibration microcontroller and sram to store calibration parameters. other system components may also be included in the calibration loop to remove offset and gain errors in the input channel using the system calibration mode. another option is a background calibration mode where the part continuously per- forms self-calibration and updates the calibration coefficients. once the part is in this mode, the user does not have to worry about issuing periodic calibration commands to the device or asking the device to recalibrate when there is a change in the ambient temperature or power supply voltage.
2 C13C rev. c AD7713 the AD7713 gives the user access to the on-chip calibration registers allowing the microprocessor to read the devices cali- bration coefficients and also to write its own calibration coeffi- cients to the part from prestored values in e 2 prom. this gives the microprocessor much greater control over the AD7713s calibration procedure. it also means that the user can verify that the device has performed its calibration correctly by comparing the coefficients after calibration with prestored values in e 2 prom. for battery operation or low power systems, the AD7713 offers a standby mode (controlled by the standby pin) that reduces idle power consumption to typically 150 m w. theory of operation the general block diagram of a sigma-delta adc is shown in figure 4. it contains the following elements: 1. a sample-hold amplifier. 2. a differential amplifier or subtracter. 3. an analog low-pass filter. 4. a 1-bit a/d converter (comparator). 5. a 1-bit dac. 6. a digital low-pass filter. s/h amp analog low-pass filter dac comparator digital filter digital data figure 4. general sigma-delta adc in operation, the analog signal sample is fed to the subtracter, along with the output of the 1-bit dac. the filtered difference signal is fed to the comparator, whose output samples the differ- ence signal at a frequency many times that of the analog signal sampling frequency (oversampling). oversampling is fundamental to the operation of sigma-delta adcs. using the quantization noise formula for an adc: snr = ( 6.02 number of bits + 1.76) db, a 1-bit adc or comparator yields an snr of 7.78 db. the AD7713 samples the input signal at a frequency of 7.8 khz or greater (see table iii). as a result, the quantization noise is spread over a much wider frequency than that of the band of interest. the noise in the band of interest is reduced still further by analog filtering in the modulator loop, which shapes the quantization noise spectrum to move most of the noise energy to frequencies outside the bandwidth of interest. the noise perfor- mance is thus improved from this 1-bit level to the performance outlined in tables i and ii and in figure 2. the output of the comparator provides the digital input for the 1-bit dac, so that the system functions as a negative feedback loop that tries to minimize the difference signal. the digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the compara- tor. it can be retrieved as a parallel binary data word using a digital filter. sigma-delta adcs are generally described by the order of the analog low-pass filter. a simple example of a first order sigma- delta adc is shown in figure 5. this contains only a first order low-pass filter or integrator. it also illustrates the derivation of the alternative name for these devices: charge balancing adcs win fs comparator differential amplifier integrator fs dac figure 5. basic charge-balancing adc it consists of a differential amplifier (whose output is the differ- ence between the analog input and the output of a 1-bit dac), an integrator and a comparator. the term charge balancing, comes from the fact that this system is a negative feedback loop that tries to keep the net charge on the integrator capacitor at zero by balancing charge injected by the input voltage with charge injected by the 1-bit dac. when the analog input is zero, the only contribution to the integrator output comes from the 1-bit dac. for the net charge on the integrator capacitor to be zero, the dac output must spend half its time at +fs and half its time at Cfs. assuming ideal components, the duty cycle of the comparator will be 50%. when a positive analog input is applied, the output of the 1-bit dac must spend a larger proportion of the time at +fs, so the duty cycle of the comparator increases. when a negative input voltage is applied, the duty cycle decreases. the AD7713 uses a second-order sigma-delta modulator and a digital filter that provides a rolling average of the sampled out- put. after power-up or if there is a step change in the input voltage, there is a settling time that must elapse before valid data is obtained. input sample rate the modulator sample frequency for the device remains at f clk in /512 (3.9 khz @ f clk in = 2 mhz) regardless of the selected gain. however, gains greater than 1 are achieved by a combination of multiple input samples per modulator cycle and a scaling of the ratio of reference capacitor to input capacitor. as a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see table iii). the ef- fective input impedance is 1/c f s where c is the input sam- pling capacitance and f s is the input sample rate. table iii. input sampling frequency vs. gain gain input sampling frequency (f s ) 1f clk in /256 (7.8 khz @ f clk in = 2 mhz) 22 f clk in /256 (15.6 khz @ f clk in = 2 mhz) 44 f clk in /256 (31.2 khz @ f clk in = 2 mhz) 88 f clk in /256 (62.4 khz @ f clk in = 2 mhz) 16 8 f clk in /256 (62.4 khz @ f clk in = 2 mhz) 32 8 f clk in /256 (62.4 khz @ f clk in = 2 mhz) 64 8 f clk in /256 (62.4 khz @ f clk in = 2 mhz) 128 8 f clk in /256 (62.4 khz @ f clk in = 2 mhz)
rev. c C14C AD7713 digital filtering the AD7713s digital filter behaves like a similar analog filter, with a few minor differences. first, since digital filtering occurs after the a-to-d conversion process, it can remove noise injected during the conversion pro- cess. analog filtering cannot do this. on the other hand, analog filtering can remove noise superim- posed on the analog signal before it reaches the adc. digital filtering cannot do this, and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. to alleviate this problem, the AD7713 has over- range headroom built into the sigma-delta modulator and digi- tal filter which allows overrange excursions of 5% above the analog input range. if noise signals are larger than this, consid- eration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. this will provide an overrange capability greater than 100% at the expense of reducing the dy- namic range by 1 bit (50%). filter characteristics the cutoff frequency of the digital filter is determined by the value loaded to bits fs0 to fs11 in the control register. at the maximum clock frequency of 2 mhz, the minimum cutoff fre- quency of the filter is 0.52 hz while the maximum program- mable cutoff frequency is 53.9 hz. figure 6 shows the filter frequency response for a cutoff fre- quency of 0.52 hz which corresponds to a first filter notch fre- quency of 2 hz. this is a (sinx/x) 3 response (also called sinc 3 ) frequency ?hz 0 ?0 ?40 012 2 gain ?dbs 4 ?60 ?80 ?00 ?20 ?0 ?40 ?0 ?0 ?20 ?00 6810 figure 6. frequency response of AD7713 filter that provides >100 db of 50 hz and 60 hz rejection. program- ming a different cutoff frequency via fs0Cfs11 does not alter the profile of the filter response; it changes the frequency of the notches as outlined in the control register section. since the AD7713 contains this on-chip, low-pass filtering, there is a settling time associated with step function inputs, and data on the output will be invalid after a step change until the settling time has elapsed. the settling time depends upon the notch frequency chosen for the filter. the output data rate equates to this filter notch frequency, and the settling time of the filter to a full-scale step input is four times the output data period. in applications using both input channels, the settling time of the filter must be allowed to elapse before data from the second channel is accessed. post filtering the on-chip modulator provides samples at a 3.9 khz output rate. the on-chip digital filter decimates these samples to pro- vide data at an output rate which corresponds to the pro- grammed first notch frequency of the filter. since the output data rate exceeds the nyquist criterion, the output rate for a given bandwidth will satisfy most application requirements. however, there may be some applications which require a higher data rate for a given bandwidth and noise performance. applications that need this higher data rate will require some post filtering following the digital filter of the AD7713. for example, if the required bandwidth is 1.57 hz but the re- quired update rate is 20 hz, the data can be taken from the AD7713 at the 20 hz rate giving a C3 db bandwidth of 5.24 hz. post filtering can be applied to this to reduce the band- width and output noise, to the 1.57 hz bandwidth level, while maintaining an output rate of 20 hz. post filtering can also be used to reduce the output noise from the device for bandwidths below 0.52 hz. at a gain of 128, the output rms noise is 250 nv. this is essentially device noise or white noise, and since the input is chopped, the noise has a flat frequency response. by reducing the bandwidth below 0.52 hz, the noise in the resultant passband can be reduced. a reduction in bandwidth by a factor of two results in a ? 2 reduction in the output rms noise. this additional filtering will result in a longer settling time. antialias considerations the digital filter does not provide any rejection at integer mul- tiples of the modulator sample frequency (n 3.9 khz, where n = 1, 2, 3 . . . ). this means that there are frequency bands, f 3 db wide (f 3 db is cutoff frequency selected by fs0 to fs11) where noise passes unattenuated to the output. however, due to the AD7713s high oversampling ratio, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. in any case, because of the high oversampling ratio a simple, rc, single pole filter is generally sufficient to attenuate the signals in these bands on the analog input and thus provide adequate antialiasing filtering. if passive components are placed in front of the ain1 and ain2 inputs of the AD7713, care must be taken to ensure that the source impedance is low enough so as not to introduce gain er- rors in the system. the dc input impedance for the ain1 and ain2 inputs is over 1 g w . the input appears as a dynamic load that varies with the clock frequency and with the selected gain (see figure 7). the input sample rate, as shown in table iii, determines the time allowed for the analog input capacitor, c in , to be charged. external impedances result in a longer charge time for this capacitor, and t his may result in gain errors being ain high impedance > 1g w r int (7k w typ) c int (11.5pf typ) switching freq depends on f clk in and selected gain v bias figure 7. ain1, ain2 input impedance
2 C15C rev. c AD7713 introduced on the analog inputs. both inputs of the differ ential input channels look into similar input circuitry. in any case, the error introduced due to longer charging times is a gain error which can be removed using the system calibration capabilities of the AD7713 provided that the resultant span is within the span limits of the system calibration techniques for the AD7713. the ain3 input contains a resistive attenuation network as out- lined in figure 8. the typical input impedance on this input is 44 k w . as a result, the ain3 input should be driven from a low impedance source. ain3 33k w 11k w v bias modulator circuit figure 8. ain3 input impedance analog input functions analog input ranges the analog inputs on the AD7713 provide the user with consid- erable flexibility in terms of analog input voltage ranges. two of the inputs are differential, programmable-gain, input channels which can handle either unipolar or bipolar input signals. the common-mode range of these inputs is from agnd to av dd provided that the absolute value of the analog input voltage lies between agnd C 30 mv and av dd + 30 mv. the third analog input is a single-ended, programmable gain high-level input which accepts analog input ranges of 0 to +4 v ref /gain. the dc input leakage current on the ain1 and ain2 inputs is 10 pa maximum at 25 c ( 1 na over temperature). this results in a dc offset voltage developed across the source impedance. however, this dc offset effect can be compensated for by a com- bination of the differential input capability of the part and its system calibration mode. the dc input current on the ain3 in- put depends on the input voltage. for the nominal input voltage range of +10 v, the input current is 225 m a typ. burn out current the ain1(+) input of the AD7713 contains a 1 m a current source which can be turned on/off via the control register. this current source can be used in checking that a transducer has not burnt out or gone open circuit before attempting to take mea- surements on that channel. if the current is turned on and is al- lowed flow into the transducer and a measurement of the input voltage on the ain1 input is taken, it can indicate that the transducer is not functioning correctly. for normal operation, this burn out current is turned off by writing a 0 to the bo bit in the control register. rtd excitation currents the AD7713 also contains two matched 200 m a constant cur- rent sources which are provided at the rtd1 and rtd2 pins of the device. these currents can be turned on/off via the control register. writing a 1 to the ro bit of the control register enables these excitation currents. for four-wire rtd applications, one of these excitation cur- rents is used to provide the excitation current for the rtd; the second current source can be left unconnected. for three-wire rtd configurations, the second on-chip current source can be used to eliminate errors due to voltage drops across lead resis- tances. figures 20 and 21 in the application section show some rtd configurations with the AD7713. the temperature coefficient of the rtd current sources is typi- cally 20 ppm/ c with a typical matching between the tempera- ture coefficients of both current sources of 3 ppm/ c. for applications where the absolute value of the temperature coeffi- cient is too large, the following schemes can be used to remove the drift error. the conversion result from the AD7713 is ratiometric to the v ref voltage. therefore, if the v ref voltage varies with the rtd temperature coefficient, the temperature drift from the current source will be removed. for four-wire rtd applications, the reference voltage can be made ratiometric to rtd current source by using the second current with a low tc resistor to generate the reference voltage for the part. in this case if a 12.5 k w resistor is used, the 200 m a current source generates +2.5 v across the resistor. this +2.5 v can be applied to the ref in(+) input of the AD7713 and the ref in(C) input at ground it will supply a v ref of 2.5 v for the part. for three-wire rtd configurations, the reference voltage for the part is gener- ated by placing a low tc resistor (12.5 k w for 2.5 v reference) in series with one of the constant current sources. the rtd current sources can be driven to within 2 v of av dd . the refer- ence input of the AD7713 is differential so the ref in(+) and ref in(C) of the AD7713 are driven from either side of the re- sistor. both schemes ensure that the reference voltage for the part tracks the rtd current sources over temperature and, thereby, removes the temperature drift error. bipolar/unipolar inputs two analog inputs on the AD7713 can accept either unipolar or bipolar input voltage ranges while the third channel accepts only unipolar signals. bipolar or unipolar options for ain1 and ain2 are chosen by programming the b/u bit of the control register. this programs both channels for either unipolar or bi- polar operation. programming the part for either unipolar or bipolar operation does not change any of the input signal condi- tioning; it simply changes the data output coding. the data cod- ing is binary for unipolar inputs and offset binary for bipolar inputs. the ain1 and ain2 input channels are differential, and as a result, the voltage to which the unipolar and bipolar signals are referenced is the voltage on the ain1(C) and ain2(C) inputs. for example, if ain1(C) is +1.25 v and the AD7713 is config- ured for unipolar operation with a gain of 1 and a v ref of +2.5 v, the input voltage range on the ain1(+) input is +1.25 v to +3.75 v. for the ain3 input, the input signals are referenced to agnd. reference input the reference inputs of the AD7713, ref in(+) and ref in(C) provide a differential reference input capability. the common-mode range for these differential inputs is from v ss to av dd . the nominal differential voltage, v ref (ref in(+) C ref in(C)), is +2.5 v for specified operation, but the reference
rev. c C16C AD7713 system synchronization if multiple AD7713s are operated from a common master clock, they can be synchronized to update their output registers simul- taneously. a falling edge on the sync input resets the filter and places the AD7713 into a consistent, known state. a com- mon signal to the AD7713s sync inputs will synchronize their operation. this would normally be done after each AD7713 has performed its own calibration or has had calibration coefficients loaded to it. the sync input can also be used to reset the digital filter in systems where the turn-on time of the digital power supply (dv dd ) is very long. in such cases, the AD7713 will start oper- ating internally before the dv dd line has reached its minimum operating level, +4.75 v. with a low dv dd voltage, the AD7713s internal digital filter logic does not operate correctly. thus, the AD7713 may have clocked itself into an incorrect operating condition by the time that dv dd has reached its cor- rect level. the digital filter will be reset upon issue of a calibra- tion command (whether it is self-calibration, system calibration or background calibration) to the AD7713. this ensures correct operation of the AD7713. in systems where the power-on de- fault conditions of the AD7713 are acceptable, and no calibra- tion is performed after power-on, issuing a sync pulse to the AD7713 will reset the AD7713s digital filter logic. an r, c on the sync line, with r, c time constant longer than the dv dd power-on time, will perform the sync function. accuracy sigma-delta adcs, like vfcs and other integrating adcs, do not contain any source of nonmonotonicity and inherently offer no missing codes performance. the AD7713 achieves excellent linearity by the use of high quality, on-chip silicon dioxide ca- pacitors, which have a very low capacitance/voltage coefficient. the device also achieves low input drift through the use of chopper stabilized techniques in its input stage. to ensure excellent perfor- mance over time and temperature, the AD7713 uses digital calibra- tion techniques that minimize offset and gain error. autocalibration autocalibration on the AD7713 removes offset and gain errors from the device. a calibration routine should be initiated on the device whenever there is a change in the ambient operating tem- perature or supply voltage. it should also be initiated if there is a change in the selected gain, filter notch or bipolar/unipolar input range. however, if the AD7713 is in its background calibration mode, the above changes are all automatically taken care of (after the settling time of the filter has been allowed for). the AD7713 offers self-calibration, system calibration and background calibration facilities. for calibration to occur on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. these are zero-scale and full-scale points. with these readings, the microcontroller can calculate the gain slope for the input to out- put transfer function of the converter. internally, the part works with a resolution of 33 bits to determine its conversion result of either 16 bits or 24 bits. voltage can go to +5 v with no degradation in performance provided that the absolute value of ref in(+) and ref in(C) does not exceed its av dd and agnd limits. the part is also functional with v ref voltages down to 1 v but with degraded performance as the output noise will, in terms of lsb size, be larger. ref in(+) must always be greater than ref in(C) for correct operation of the AD7713. both reference inputs provide a high impedance, dynamic load similar to the analog inputs. the maximum dc input leakage current is 10 pa ( 1 na over temperature) and source resis- tance may result in gain errors on the part. the reference inputs look like the ain1 analog input (see figure 7). in this case, r int is 5 k w typ and c int varies with gain. the input sample rate is f clk in /256 and does not vary with gain. for gains of 1 to 8 c int is 20 pf; for a gain of 16 it is 10 pf; for a gain of 32 it is 5 pf; for a gain of 64 it is 2.5 pf; and for a gain of 128 it is 1.25 pf. the digital filter of the AD7713 removes noise from the refer- ence input just as it does with the analog input, and the same limitations apply regarding lack of noise rejection at integer mul- tiples of the sampling frequency. the output noise performance outlined in tables i and ii assumes a clean reference. if the ref- erence noise in the bandwidth of interest is excessive, it can degrade the performance of the AD7713. a recommended refer- ence source for the AD7713 is the ad680, a 2.5 v reference. using the AD7713 system design considerations the AD7713 operates differently from successive approximation adcs or integrating adcs. since it samples the signal continu- ously, like a tracking adc, there is no need for a start convert command. the output register is updated at a rate determined by the first notch of the filter and the output can be read at any time, either synchronously or asynchronously. clocking the AD7713 requires a master clock input, which may be an external ttl/cmos compatible clock signal applied to the mclk in pin with the mclk out pin left unconnected. alternatively, a crystal of the correct frequency can be con- nected between mclk in and mclk out, in which case the clock circuit will function as a crystal controlled oscillator. for lower clock frequencies, a ceramic resonator may be used in- stead of the crystal. for these lower frequency oscillators, exter- nal capacitors may be required on either the ceramic resonator or on the crystal. the input sampling frequency, the modulator sampling fre- quency, the C3 db frequency, output update rate and calibration time are all directly related to the master clock frequency, f clk in. reducing the master clock frequency by a factor of two will halve the above frequencies and update rate and will double the calibration time. the current drawn from the dv dd power supply is also directly related to f clk in . reducing f clk in by a factor of two will halve the dv dd current but will not affect the current drawn from the av dd power supply.
2 C17C rev. c AD7713 the AD7713 also provides the facility to write to the on-chip calibration registers, and in this manner the span and offset for the part can be adjusted by the user. the offset calibration regis- ter contains a value which is subtracted from all conversion results, while the full-scale calibration register contains a value which is multiplied by all conversion results. the offset calibra- tion coefficient is subtracted from the result prior to the multi- plication by the full-scale coefficient. in the first three modes outlined here, the drdy line indicates that calibration is com- plete by going low. if drdy is low before (or goes low during) the calibration command, it may take up to one modulator cycle before drdy goes high to indicate that calibration is in progress. therefore, the drdy line should be ignored for up to one modulator cycle after the last bit of the calibration com- mand is written to the control register. self-calibration in the self-calibration mode with a unipolar input range, the zero-scale point used in determining the calibration coefficients is with both inputs shorted (i.e., ain1(+) = ain1(C) = v bias for ain1 and ain2 and ain3 = v bias for ain3 ) and the full-scale point is v ref . the zero-scale coefficient is determined by converting an internal shorted inputs node. the full-scale co- efficient is determined from the span between this shorted in- puts conversion and a conversion on an internal v ref node. the self-calibration mode is invoked by writing the appropriate val- ues (0, 0, 1) to the md2, md1 and md0 bits of the control register. in this calibration mode, the shorted inputs node is switched in to the modulator first and a conversion is performed; the v ref node is then switched in, and another conversion is per- formed. when the calibration sequence is complete, the calibration coefficients updated and the filter resettled to the analog input voltage, the drdy output goes low. the self-calibration proce- dure takes into account the selected gain on the pga. for bipolar input ranges in the self-calibrating mode, the sequence is very similar to that just outlined. in this case, the two points that the AD7713 calibrates are midscale (bipolar zero) and positive full scale. system calibration system calibration allows the AD7713 to compensate for system gain and offset errors as well as its own internal errors. system calibration performs the same slope factor calculations as self- calibration but uses voltage values presented by the system to the ain inputs for the zero and full-scale points. system cali- bration is a two-step process. the zero-scale point must be pre- sented to the converter first. it must be applied to the converter before the calibration step is initiated and remain stable until the step is complete. system calibration is initiated by writing the appropriate values (0, 1, 0) to the md2, md1 and md0 bits of the control register. the drdy output from the device will sig- nal when the step is complete by going low. after the zero-scale point is calibrated, the full-scale point is applied and the second step of the calibration process is initiated by again writing the appropriate values (0, 1, 1) to md2, md1 and md0. again the full-scale voltage must be set up before the calibration is initi- ated, and it must remain stable throughout the calibration step. drdy goes low at the end of this second step to indicate that the system calibration is complete. in the unipolar mode, the system calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed be- tween midscale and positive full scale. this two-step system calibration mode offers another feature. after the sequence has been completed, additional offset or gain calibrations can be performed by themselves to adjust the zero reference point or the system gain. this is achieved by perform- ing the first step of the system calibration sequence (by writing 0, 1, 0 to md2, md1, md0). this will adjust the zero-scale or offset point but will not change the slope factor from what was set during a full system calibration sequence. system calibration can also be used to remove any errors from an antialiasing filter on the analog input. a simple r, c anti- aliasing filter on the front end may introduce a gain error on the analog input voltage but the system calibration can be used to remove this error. system offset calibration system offset calibration is a variation of both the system cali- bration and self-calibration. in this case, the zero-scale point for the system is presented to the ain input of the converter. system offset calibration is initiated by writing 1, 0, 0 to md2, md1, md0. the system zero-scale coefficient is determined by converting the voltage applied to the ain input, while the full- scale coefficient is determined from the span between this ain conversion and a conversion on v ref . the zero-scale point should be applied to the ain input for the duration of the cali- bration sequence. this is a one-step calibration sequence with drdy going low when the sequence is completed. in the uni- polar mode, the system offset calibration is performed between the two endpoints of the transfer function; in the bipolar mode, it is performed between midscale and positive full scale. background calibration the AD7713 also offers a background calibration mode where the part interleaves its calibration procedure with its normal conversion sequence. in the background calibration mode, the same voltages are used as the calibration points as are used in the self-calibration mode, i.e., shorted inputs and v ref . the background calibration mode is invoked by writing 1, 0, 1 to md2, md1, md0 of the control register. when invoked, the background calibration mode reduces the output data rate of the AD7713 by a factor of six while the C3 db bandwidth remains unchanged. its advantage is that the part is continually perform- ing calibration and automatically updating its calibration coeffi- cients. as a result, the effects of temperature drift, supply sensitivity and time drift on zero- and full-scale errors are automatically removed. when the background calibration mode is turned on, the part will remain in this mode until bits md2, md1 and md0 of the control register are changed. with background cali- bration mode on, the first result from the AD7713 will be incor- rect as the full-scale calibration will not have been performed. for a step change on the input, the second output update will have settled to 100% of the final value. table iv summarizes the calibration modes and the calibration points associated with them. it also gives the duration from when the calibration is invoked to when valid data is available to the user.
rev. c C18C AD7713 table iv. calibration truth table cal type md2, md1, md0 zero-scale cal full-scale cal sequence duration self-cal 0, 0, 1 shorted inputs v ref one step 9 1/output rate system cal 0, 1, 0 ain two step 4 1/output rate system cal 0, 1, 1 ain two step 4 1/output rate system offset cal 1, 0, 0 ain v ref one step 9 1/output rate background cal 1, 0, 1 shorted inputs v ref one step 6 1/output rate span and offset limits whenever a system calibration mode is used, there are limits on the amount of offset and span that can be accommodated. the range of input span in both the unipolar and bipolar modes for ain1 and ain2 has a minimum value of 0.8 v ref /gain and a maximum value of 2.1 v ref /gain. for ain3, the mini- mum value is 3.2 v ref /gain while the maximum value is 4.2 v ref /gain. the amount of offset which can be accommodated depends on whether the unipolar or bipolar mode is being used. this offset range is limited by the requirement that the positive full-scale calibration limit is 1.05 v ref /gain for ain1 and ain2. therefore, the offset range plus the span range cannot exceed 1.05 v ref /gain for ain1 and ain2. if the span is at its minimum (0.8 v ref /gain) the maximum the offset can be is (0.25 v ref /gain) for ain1 and ain2. for ain3, both ranges are multiplied by a factor of four. in the bipolar mode, the system offset calibration range is again restricted by the span range. the span range of the converter in bipolar mode is equidistant around the voltage used for the zero-scale point, thus the offset range plus half the span range cannot exceed (1.05 v ref /gain) for ain1 and ain2. if the span is set to 2 v ref /gain, the offset span cannot move more than (0.05 v ref /gain) before the endpoints of the transfer function exceed the input overrange limits (1.05 v ref /gain) for ain1. if the span range is set to the minimum (0.4 v ref /gain), the maximum allowable offset range is (0.65 v ref /gain) for ain1 and ain2. the ain3 input can only be used in the unipolar mode.. power-up and calibration on power-up, the AD7713 performs an internal reset which sets the contents of the control register to a known state. however, to ensure correct calibration for the device a calibration routine should be performed after power-up. the power dissipation and temperature drift of the AD7713 are low and no warm-up time is required before the initial calibra- tion is performed. however, the external reference must have stabilized before calibration is initiated. drift considerations the AD7713 uses chopper stabilization techniques to minimize input offset drift. charge injection in the analog switches and dc leakage currents at the sampling node are the primary sources of offset voltage drift in the converter. the dc input leakage cur- rent is essentially independent of the selected gain. gain drift within the converter depends primarily upon the temperature tracking of the internal capacitors. it is not affected by leakage currents. measurement errors due to offset drift or gain drift can be elimi- nated at any time by recalibrating the converter or by operating the part in the background calibration mode. using the system calibration mode can also minimize offset and gain errors in the signal conditioning circuitry. integral and differential linearity errors are not significantly affected by temperature changes. power supplies and grounding the analog and digital supplies to the AD7713 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the digital filter will provide rejection of broadband noise on the power supplies, ex- cept at integer multiples of the modulator sampling frequency. the digital supply (dv dd ) must not exceed the analog positive supply (av dd ) by more than 0.3 v. if separate analog and digi- tal supplies are used, the recommended decoupling scheme is shown in figure 9. in systems where av dd = +5 v and dv dd = +5 v, it is recommended that av dd and dv dd are driven from the same +5 v supply, although each supply should be de- coupled separately as shown in figure 9. it is preferable that the common supply is the systems analog +5 v supply. it is also important that power is applied to the AD7713 before signals at ref in, ain or the logic input pins in order to avoid excessive current. if separate supplies are used for the AD7713 and the system digital circuitry, then the AD7713 should be powered up first. if it is not possible to guarantee this, then cur- rent limiting resistors should be placed in series with the logic inputs. AD7713 0.1? 0.1? 10? av dd dv dd analog supply digital +5v supply figure 9. recommended decoupling scheme
2 C19C rev. c AD7713 output data register. it is reset high when the last bit of data (either 16th bit or 24th bit) is read from the output register. if data is not read from the output register, the drdy line will remain low. the output register will continue to be updated at the output update rate but drdy will not indicate this. a read from the device in this circumstance will access the most recent word in the output register. if a new data word becomes avail- able to the output register while data is being read from the out- put register, drdy will not indicate this and the new data word will be lost to the user. drdy is not affected by reading from the control register or the calibration registers. data can only be accessed from the output data register when drdy is low. if rfs goes low with drdy high, no data trans- fer will take place. drdy does not have any effect on reading data from the control register or from the calibration registers. figure 10 shows a timing diagram for reading from the AD7713 in the self-clocking mode. this read operation shows a read from the AD7713s output data register. a read from the con- trol register or calibration registers is similar, but in these cases the drdy line is not related to the read function. depending on the output update rate, it can go low at any stage in the con- trol/calibration register read cycle without affecting the read and its status should be ignored. a read operation from either the control or calibration registers must always read 24 bits of data from the respective register. figure 10 shows a read operation from the AD7713. for the timing diagram shown, it is assumed that there is a pull-up resis- tor on the sclk output. with drdy low, the rfs input is brought low. rfs going low enables the serial clock of the AD7713 and also places the msb of the word on the serial data line. all subsequent data bits are clocked out on a high to low transition of the serial clock and are valid prior to the following rising edge of this clock. the final active falling edge of sclk clocks out the lsb, and this lsb is valid prior to the final active rising edge of sclk. coincident with the next falling edge of sclk, drdy is reset high. drdy going high turns off the sclk and the sdata outputs. this means that the data hold time for the lsb is slightly shorter than for all other bits. digital interface the AD7713s serial communications port provides a flexible arrangement to allow easy interfacing to industry-standard microprocessors, microcontrollers and digital signal processors. a serial read to the AD7713 can access data from the output register, the control register or from the calibration registers. a serial write to the AD7713 can write data to the control register or the calibration registers. two different modes of operation are available, optimized for different types of interface where the AD7713 can act either as master in the system (it provides the serial clock) or as slave (an external serial clock can be provided to the AD7713). these two modes, labelled self-clocking mode and external clocking mode, are discussed in detail in the following sections. self-clocking mode the AD7713 is configured for its self-clocking mode by tying the mode pin high. in this mode, the AD7713 provides the serial clock signal used for the transfer of data to and from the AD7713. this self-clocking mode can be used with processors that allow an external device to clock their serial port including most digital signal processors and microcontrollers such as the 68hc11 and 68hc05. it also allows easy interfacing to serial parallel conversion circuits in systems with parallel data commu- nication, allowing interfacing to 74xx299 universal shift regis- ters without any additional decoding. in the case of shift registers, the serial clock line should have a pull-down resistor instead of the pull-up resistor shown in figure 10 and figure 11. read operation data can be read from either the output register, the control register or the calibration registers. a0 determines whether the data read accesses data from the control register or from the output/calibration registers. this a0 signal must remain valid for the duration of the serial read operation. with a0 high, data is accessed from either the output register or from the calibra- tion registers. with a0 low, data is accessed from the control register. the function of the drdy line is dependent only on the output update rate of the device and the reading of the output data reg- ister. drdy goes low when a new data word is available in the 3-state sdata (o) sclk (o) rfs (i) a0 (i) drdy (o) msb lsb t 3 t 2 t 4 t 5 t 6 t 9 t 10 t 8 t 7 figure 10. self-clocking mode, output data read operation
rev. c C20C AD7713 sdata (i) sclk (o) tfs (i) a0 (i) msb lsb t 14 t 9 t 15 t 16 t 17 t 18 t 19 t 10 figure 11. self-clocking mode, control/calibration register write operation write operation data can be written to either the control register or calibration registers. in either case, the write operation is not affected by the drdy line and the write operation does not have any effect on the status of drdy . a write operation to the control register or the calibration register must always write 24 bits to the respective register. figure 11 shows a write operation to the AD7713. a0 deter- mines whether a write operation transfers data to the control register or to the calibration registers. this a0 signal must re- main valid for the duration of the serial write operation. the falling edge of tfs enables the internally generated sclk out- put. the serial data to be loaded to the AD7713 must be valid on the rising edge of this sclk signal. data is clocked into the AD7713 on the rising edge of the sclk signal with the msb transferred first. on the last active high time of sclk, the lsb is loaded to the AD7713. subsequent to the next falling edge of sclk, the sclk output is turned off. (the timing diagram of figure 11 assumes a pull-up resistor on the sclk line.) external clocking mode the AD7713 is configured for its external clocking mode by tying the mode pin low. in this mode, sclk of the AD7713 is configured as an input, and an external serial clock must be provided to this sclk pin. this external clocking mode is designed for direct interface to systems which provide a serial clock output which is synchronized to the serial data output, including microcontrollers such as the 80c51, 87c51, 68hc11 and 68hc05 and most digital signal processors. read operation as with the self-clocking mode, data can be read from either the output register, the control register or the calibration registers. a0 determines whether the data read accesses data from the control register or from the output/calibration registers. this a0 signal must remain valid for the duration of the serial read op- eration. with a0 high, data is accessed from either the output register or from the calibration registers. with a0 low, data is accessed from the control register. the function of the drdy line is dependent only on the output update rate of the device and the reading of the output data reg- ister. drdy goes low when a new data word is available in the output data register. it is reset high when the last bit of data (either 16th bit or 24th bit) is read from the output register. if data is not read from the output register, the drdy line will remain low. the output register will continue to be updated at the output update rate, but drdy will not indicate this. a read from the device in this circumstance will access the most recent word in the output register. if a new data word becomes avail- able to the output register while data is being read from the out- put register, drdy will not indicate this and the new data word will be lost to the user. drdy is not affected by reading from the control register or the calibration register. data can only be accessed from the output data register when drdy is low. if rfs goes low while drdy is high, no data transfer will take place. drdy does not have any effect on reading data from the control register or from the calibration regis- ters. figures 12a and 12b show timing diagrams for reading from the AD7713 in the external clocking mode. figure 12a shows a situation where all the data is read from the AD7713 in one read operation. figure 12b shows a situation where the data is read from the AD7713 over a number of read operations. both read operations show a read from the AD7713s output data register. a read from the control register or c alibration registers is similar, but in these cases the drdy line is not related to the read function. depending on the output update rate, it can go low at any stage in the control/calibration register read cycle without affecting the read and its status should be ignored. a read operation from either the control or calibration registers must always read 24 bits of data from the respective register. figure 12a shows a read operation from the AD7713 where rfs remains low for the duration of the data word transmis- sion. with drdy low, the rfs input is brought low. the in- put sclk signal should be low between read and write operations. rfs going low places the msb of the word to be read on the serial data line. all subsequent data bits are clocked out on a high to low transition of the serial clock and are valid prior to the following rising edge of this clock. the penultimate falling edge of sclk clocks out the lsb and the final falling edge resets the drdy line high. this rising edge of drdy turns off the serial data output. figure 12b shows a timing diagram for a read operation where rfs returns high during the transmission of the word and re- turns low again to access the rest of the data word. timing parameters and functions are very similar to that outlined for figure 12a, but figure 12b has a number of additional times to show timing relationships when rfs returns high in the middle of transferring a word. rfs should return high during a low time of sclk. on the rising edge of rfs , the sdata output is turned off. drdy remains low and will remain low until all bits of the data word are read from the AD7713, regardless of the number of times rfs changes state during the read operation. depending on the time between the falling edge of sclk and the rising edge of
2 C21C rev. c AD7713 sdata (o) sclk (i) 3-state rfs (i) a0 (i) t 22 msb lsb drdy (o) t 21 t 20 t 23 t 26 t 29 t 28 t 27 t 25 t 24 figure 12a. external clocking mode, output data read operation 3-state msb bit n bit n+1 sdata (o) sclk (i) rfs (i) a0 (i) drdy (o) t 22 t 20 t 31 t 26 t 24 t 25 t 27 t 30 t 24 t 25 figure 12b. external clocking mode, output data read operation ( rfs returns high during read operation) rfs , the next bit (bit n + 1) may appear on the databus be- fore rfs goes high. when rfs returns low again, it activates the sdata output. when the entire word is transmitted, the drdy line will go high, turning off the sdata output as per figure 12a. write operation data can be written to either the control register or calibration registers. in either case, the write operation is not affected by the drdy line, and the write operation does not have any effect on the status of drdy . a write operation to the control regis- ter or the calibration register must always write 24 bits to the re- spective register. figure 13a shows a write operation to the AD7713 with tfs remaining low for the duration of the write operation. a0 deter- mines whether a write operation transfers data to the control register or to the calibration registers. this a0 signal must remain valid for the duration of the serial write operation. as before, the serial clock line should be low between read and write operations. the serial data to be loaded to the AD7713 must be valid on the high level of the externally applied sclk signal. data is clocked into the AD7713 on the high level of this sclk signal with the msb transferred first. on the last active high time of sclk, the lsb is loaded to the AD7713. figure 13b shows a timing diagram for a write operation to the AD7713 with tfs returning high during the write operation and returning low again to write the rest of the data word. tim- ing parameters and functions are very similar to that outlined for figure 13a, but figure 13b has a number of additional times to show timing relationships when tfs returns high in the middle of transferring a word. sclk (i) sdata (i) tfs (i) a0 (i) msb lsb t 32 t 33 t 34 t 26 t 27 t 36 t 35 figure 13a. external clocking mode, control/calibration register write operation
rev. c C22C AD7713 sclk (i) sdata (i) tfs (i) a0 (i) msb bit n bit n+1 t 32 t 26 t 30 t 27 t 36 t 35 t 35 t 36 figure 13b. external clocking mode, control/calibration register write operation ( tfs returns high during write operation) data to be loaded to the AD7713 must be valid prior to the ris- ing edge of the sclk signal. tfs should return high during the low time of sclk. after tfs returns low again, the next bit of the data word to be loaded to the AD7713 is clocked in on next high level of the sclk input. on the last active high time of the sclk input, the lsb is loaded to the AD7713. simplifying the external clocking mode interface in many applications, the user may not require the facility of writing to the on-chip calibration registers. in this case, the serial interface to the AD7713 in external clocking modecan be simplified by connecting the tfs line to the a0 input of the AD7713 (see figure 14). this means that any write to the de- vice will load data to the control register (since a0 is low while tfs is low) and any read to the device will access data from the output data register or from the calibration registers (since a0 is high while rfs is low). it should be noted that in this arrange- ment the user does not have the capability of reading from the control register. four interface lines rfs AD7713 sdata sclk tfs a0 figure 14. simplified interface with tfs connected to a0 another method of simplifying the interface is to generate the tfs signal from an inverted rfs signal. however, generating the signals the opposite way around ( rfs from an inverted tfs ) will cause writing errors. microcomputer/microprocessor interfacing the AD7713s flexible serial interface allows for easy interface to most microcomputers and microprocessors. figure 15 shows a flowchart diagram for a typical programming sequence for reading data from the AD7713 to a microcomputer while figure 16 shows a flowchart diagram for writing data to the AD7713. figures 17, 18 and 19 show some typical interface circuits. the flowchart of figure 15 is for continuous read operations from the AD7713 output register. in the example shown, the drdy line is continuously polled. depending on the micropro- cessor configuration, the drdy line may come to an interrupt input in which case the drdy will automatically generate an interrupt without being polled. the reading of the serial buffer could be anything from one read operation up to three read start configure & initialize ?/? serial port no yes x3 bring rfs low reverse order of bits drdy low? bring rfs , tfs high poll drdy read serial buffer bring rfs high figure 15. flowchart for continuous read operations to the AD7713
2 C23C rev. c AD7713 operations (where 24 bits of data are read into an 8-bit serial register). a read operation to the control/calibration registers is similar, but in this case the status of drdy can be ignored. the a0 line is brought low when the rfs line is brought low when reading from the control register. the flowchart also shows the bits being reversed after they have been read in from the serial port. this depends on whether the microprocessor expects the msb of the word first or the lsb of the word first. the AD7713 outputs the msb first. the flowchart for figure 16 is for a single 24-bit write operation to the AD7713 control or calibration registers. this shows data being transferred from data memory to the accumulator before being written to the serial buffer. some microprocessor systems will allow data to be written directly to the serial buffer from data memory. the writing of data to the serial buffer from the accumulator will generally consist of either two or three write operations, depending on the size of the serial buffer. the flowchart also shows the option of the bits being reversed before being written to the serial buffer. this depends on whether the first bit transmitted by the microprocessor is the msb or the lsb. the AD7713 expects the msb as the first bit in the data stream. in cases where the data is being read or be- ing written in bytes and the data has to be reversed, the bits will have to be reversed for every byte. end start configure & initialize ?/? serial port x3 bring rfs & a0 low reverse order of bits bring rfs , tfs & a0 high load data from address to accumulator write data from accumulator to serial buffer bring tfs & a0 high figure 16. flowchart for single write operation to the AD7713 AD7713 to 8051 interface figure 17 shows an interface between the AD7713 and the 8xc51 microcontroller. the AD7713 is configured for its exter- nal clocking mode while the 8xc51 is configured in its mode 0 serial interface mode. the drdy line from the AD7713 is con- nected to the port p1.2 input of the 8xc51 so the drdy line is polled by the 8xc51. the drdy line can be connected to the int1 input of the 8xc51 if an interrupt driven system is preferred. rfs AD7713 sdata sclk tfs a0 p1.0 p3.0 p3.1 p1.1 p1.2 mode drdy p1.3 sync dv dd 8xc51 figure 17. AD7713 to 8xc51 interface table v shows some typical 8xc51 code used for a single 24-bit read from the output register of the AD7713. table v shows some typical code for a single write operation to the con- trol register of the AD7713. the 8xc51 outputs the lsb first in a write operation while the AD7713 expects the msb first, so the data to be transmitted has to be rearranged before being written to the output serial register. similarly, the AD7713 out- puts the msb first during a read operation while the 8xc51 expects the lsb first. therefore, the data which is read into the serial buffer needs to be rearranged before the correct data word from the AD7713 is available in the accumulator. table v. 8xc51 code for reading from the AD7713 mov scon,#00010001b; configure 8051 for mode 0 mov ie,#00010000b; disable all interrupts setb 90h; set p1.0, used as rfs setb 91h; set p1.1, used as tfs setb 93h; set p1.3, used as a0 mov r1,#003h; s ets number of bytes to be read in a read operation mov r0,#030h; start address for where bytes will be loaded mov r6,#004h; use p1.2 as drdy wait: nop; mov a,p1; read port 1 anl a,r6; mask out all bits except drdy jz read; if zero read sjmp wait; otherwise keep polling read: clr 90h; bring rfs low clr 98h; clear receive flag poll: jb 98h, read1 tests receive interrupt flag sjmp poll continued on next page
rev. c C24C AD7713 which is in its single chip mode. the drdy line from the AD7713 is connected to the port pc0 input of the 68hc11 so the drdy line is polled by the 68hc11. the drdy line can be connected to the irq input of the 68hc11 if an interrupt driven system is preferred. the 68hc11 mosi and miso lines should be configured for wired-or operation. depending on the interface configuration, it may be necessary to provide bidirec- tional buffers between the 68hc11s mosi and miso lines. the 68hc11 is configured in the master mode with its cpol bit set to a logic zero and its cpha bit set to a logic one. dv dd sync rfs tfs a0 sdata sclk mode pc0 pc1 pc2 pc3 miso mosi 68hc11 AD7713 drdy ss sck dv dd figure 18. AD7713 to 68hc11 interface AD7713 to adsp-2105 interface an interface circuit between the AD7713 and the adsp-2105 microprocessor is shown in figure 19. in this interface, the AD7713 is configured for its self-clocking mode while the rfs and tfs pins of the adsp-2105 are configured as inputs and the adsp-2105 serial clock line is also configured as an input. when the adsp-2105s serial clock is configured as an input it needs a couple of clock pulses to initialize itself correctly before accepting data. therefore, the first read from the AD7713 may not read correct data. in the interface shown, a read operation to the AD7713 accesses either the output register or the calibra- tion registers. data cannot be read from the control register. a write operation always writes to the control or calibration registers. drdy is used as the frame synchronization pulse for read op- erations from the output register and it is decoded with a0 to drive the rfs inputs of both the AD7713 and the adsp-2105. the latched a0 line drives the tfs inputs of both the AD7713 and the adsp-2105 as well as the AD7713 a0 input. dv dd a0 sdata sclk mode a0 dr adsp-2105 AD7713 rfs tfs drdy rfs tfs 74hc74 q d q dt sclk dmwr figure 19. AD7713 to adsp-2105 interface read 1: mov a,sbuf; read buffer rlc a; rearrange data mov b.0,c; reverse order of bits rlc a; mov b.1,c; rlc a; mov b.2,c; rlc a; mov b.3,c; rlc a; mov b.4,c; rlc a; mov b.5,c; rlc a; mov b.6,c; rlc a; mov b.7,c; mov a,b; mov @r0,a; write data to memory inc r0; increment memory location dec r1 decrement byte counter mov a,r1 jz end jump if zero jmp wait fetch next byte end: setb 90h bring rfs high fin: sjmp fin table vi. 8xc51 code for writing to the AD7713 mov scon,#00000000b; configure 8051 for mode 0 operation & enable serial reception mov ie,#10010000b; enable transmit interrupt mov ip,#00010000b; prioritize the transmit interrupt setb 91h; bring tfs high setb 90h; bring rfs high mov r1,#003h; sets number of bytes to be written in a write operation mov r0,#030h; start address in ram for bytes mov a,#00h; clear accumulator mov sbuf,a; initialize the serial port wait: jmp wait; wait for interrupt int routine: nop; interrupt subroutine mov a,r1; load r1 to accumulator jz fin; if zero jump to fin dec r1; decrement r1 byte counter mov a,@r; move byte into the accumulator inc r0; increment address rlc a; rearrange datafrom lsb first to msb first mov b.0,c; rlc a; mov b.1,c; rlc a; mov b.2,c; rlc a; mov b.3,c; rlc a; mov b.4,c; rlc a; mov b.5,c; rlc a; mov b.6,c; rlc a: mov b.7,c; mov a,b; clr 93h; bring a0 low clr 91h; bring tfs low mov sbuf,a; write to serial port reti; return from subroutine fin: setb 91h; set tfs high setb 93h; set a0 high reti; return from interrupt subroutine AD7713 to 68hc11 interface figure 18 shows an interface between the AD7713 and the 68hc11 microcontroller. the AD7713 is configured for its ex- ternal clocking mode while the spi port is used on the 68hc11
2 C25C rev. c AD7713 applications four-wire rtd configurations figure 20 shows a four-wire rtd application where the rtd transducer is interfaced directly to the AD7713. in the four-wire configuration, there are no errors associated with lead resis- tances as no current flows in the measurement leads connected to ain1(+) and ain1(C). one of the rtd current sources is used to provide the excitation current for the rtd. a common nominal resistance value for the rtd is 100 w and, therefore, the rtd will generate a 20 mv signal which can be handled di- rectly by the analog input of the AD7713. in the circuit shown, the second rtd excitation current is used to generate the refer- ence voltage for the AD7713. this reference voltage is devel- oped across r ref and applied to the differential reference inputs. for the nominal reference voltage of +2.5 v, r ref is 12.5 k w . this scheme ensures that the analog input voltage span remains ratiometric to the reference voltage. any errors in the analog input voltage due to the temperature drift of the rtd current source is compensated for by the variation in the refer- ence voltage. the typical matching between the two rtd cur- rent sources is less than 3 ppm/ c. ain1(+) ain1(? av dd agnd dgnd a = 1 ?128 AD7713 rtd1 rtd ref in(+) ref in(? rtd2 200? +5v r ref internal circuitry dv dd 200? pga figure 20. four-wire rtd application with the AD7713 three-wire rtd configurations figure 21 shows a three-wire rtd configuration using the AD7713. in the three-wire configuration, the lead resistances will result in errors if only one current source is used as the 200 m a will flow through r l1 developing a voltage error between ain1(+) and ain1(C). in the scheme outlined below, the sec- ond rtd current source is used to compensate for the error in- troduced by the 200 m a flowing through r l1 . the second rtd current flows through r l2 . assuming r l1 and r l2 are equal (the leads would normally be of the same material and of equal length) and rtd1 and rtd2 match, then the error voltage across r l2 equals the error voltage across r l1 and no error volt- age is developed between ain1(+) and ain1(C). twice the voltage is developed across r l3 but since this is a common-mode voltage it will not introduce any errors. the reference voltage is derived from one of the current sources. this gives all the bene- fits of eliminating rtd tempco errors as outlined in figure 20. the voltage on either rtd input can go to within 2 v of the av dd supply. the circuit is shown for a +2.5 v reference. ain(+) ain(? av dd dv dd agnd dgnd a = 1 ?128 AD7713 rtd1 rtd2 rtd 12.5k w internal circuitry ref in(+) ref in(? 200? pga r l1 r l2 r l3 200? figure 21. three-wire rtd application with the AD7713 4C20 ma loop the AD7713s high level input can be used to measure the cur- rent in 4C20 ma loop applications as shown in figure 22. in this case, the system calibration capabilities of the AD7713 can be used to remove the offset caused by the 4 ma flowing through the 500 w resistor. the AD7713 can handle an input span as low as 3.2 v ref (= 8 v with a v ref of +2.5 v) even though the nominal input voltage range for the input is 10 v. therefore, the full span of the a/d converter can be used for measuring the current between 4 ma and 20 ma. ref in(+) ain1(+) ain1(? ain3 agnd dgnd a = 1 ?128 1? ref in(? AD7713 4?0ma loop analog +5v supply 500 w voltage attenuation av dd av dd dv dd internal circuitry m u x pga figure 22. 4C20 ma measurement using the AD7713
rev. c C26C AD7713 other 24-bit signal conditioning adcs available from analog devices functional block diagram clock generation serial interface control register output register charging balancing a/d converter auto-zeroed ? - d modulator digital filter ad7710 m u x agnd dgnd mode sdata sclk a0 mclk out mclk in ain1(+) ain1(? ain2(+) ain2(? ref in(? ref in(+) av dd dv dd av dd 4.5? a = 1 ?128 v ss av dd 20? v bias ref out sync drdy tfs rfs rtd current 2.5v reference pga functional block diagram clock generation serial interface control register output register charging balancing a/d converter auto-zeroed ? - d modulator digital filter ad7711 m u x agnd dgnd mode sdata sclk a0 mclk out mclk in ain1(+) ain1(? ain2 ref in(? ref in(+) av dd dv dd av dd 4.5? a = 1 ?128 v ss av dd 200? v bias ref out sync drdy tfs rfs rtd2 2.5v reference pga 200? rtd1 ad7710 features charge balancing adc 24 bits no missing codes 6 0.0015% nonlinearity two-channel programmable gain front end gains from 1 to 128 differential inputs low-pass filter with programmable filter cutoffs ability to read/write calibration coefficients bidirectional microcontroller serial interface internal/external reference option single or dual supply operation low power (25 mw typ) with power-down mode (7 mw typ} applications weigh scales thermocouples process control smart transmitters chromatography ad7711 features charge balancing adc 24 bits no missing codes 6 0.0015% nonlinearity two-channel programmable gain front end gains from 1 to 128 one differential input one single-ended input low-pass filter with programmable filter cutoffs ability to read/write calibration coefficients rtd excitation current sources bidirectional microcontroller serial interface internal/external reference option single or dual supply operation low power (25 mw typ) with power-down mode (7 mw typ) applications rtd transducers process control smart transmitters portable industrial instruments
2 C27C rev. c AD7713 ad7712 features charge balancing adc 24 bits no missing codes 6 0.0015% nonlinearity high level and low level analog input channels programmable gain for both inputs gains from 1 to 128 differential input for low level channel low-pass filter with programmable filter cutoffs ability to read/write calibration coefficients bidirectional microcontroller serial interface internal/external reference option single or dual supply operation low power (25 mw typ) with power-down mode (100 m w typ} applications process control smart transmitters portable industrial instruments functional block diagram clock generation serial interface control register output register charging balancing a/d converter auto-zeroed ? - d modulator digital filter ad7712 m u x agnd dgnd mode sdata sclk a0 mclk out mclk in ain1(+) ain1(? ref in(? ref in(+) av dd dv dd av dd 4.5? a = 1 ?128 v ss v bias ref out sync drdy tfs rfs ain2 2.5v reference pga voltage attenuation tp standby
rev. c C28C AD7713 outline dimensions dimensions are shown in inches and (mm). plastic dip (n-24) 0.210 (5.33) max 0.280 (7.11) 0.240 (6.10) 12 13 24 1 0 - 15 0.100 (2.54) bsc seating plane 0.150 (3.81) min 1.275 (32.30) 1.125 (28.60) 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) cerdip (q-24) 0.005 (0.13) min 0.098 (2.49) max 1.280 (32.51) max 0.150 (3.81) min 0.200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.310 (7.87) 0.220 (5.59 0 ?15 0.015 (0.38) 0.008 (0.20) seating plane 0.060 (1.52) 0.015 (0.38) 12 1 13 24 0.070 (1.78) 0.030 (0.76) 0.110 (2.79) 0.090 (2.29) 0.320 (8.13) 0.290 (7.37) soic (r-24) 112 13 24 15.6 (0.614) 15.2 (0.598) 0.299 (7.6) 0.291 (7.4) 0.419 (10.65) 0.394 (10.00) 0.050 (1.27) bsc 0.019 (0.49) 0.014 (0.35) 0.104 (2.65) 0.093 (2.35) 0.012 (0.3) 0.004 (0.1) 0.050 (1.27) 0.016 (0.40) 0.013 (0.32) 0.009 (0.23) c1657bC5C7/95 printed in u.s.a.

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